`timescale 10ns/1ps

module IMEM_test;

	reg iClk; 		// clock
	reg iWe;		// write enable
	reg [7:2] iAddr;	// adrress
	reg [31:0] iWdata;	// write data
	wire [31:0] oRdata;	

	IMEM M0 (.*);

	initial
	begin
		iClk = 1'b0;
		forever #0.5 iClk=~iClk;
	end

	initial
	fork
		iAddr <= 6'b000010;
		#3 iAddr <= 6'b100010;
		#3 iWdata <= 32'b0101010101010101010101;
		#3 iWe <= 1'b1;
		#6 iAddr <= 6'b100010;
	join
endmodule
